The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Feb. 28, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Michael Todd Wyant, Dallas, TX (US);

Joseph Liu, Dallas, TX (US);

Christopher Daniel Manack, Flower Mound, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/544 (2006.01); H01L 23/10 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 23/31 (2013.01); H01L 23/544 (2013.01); H01L 22/34 (2013.01); H01L 23/10 (2013.01);
Abstract

In some examples, a method for manufacturing a semiconductor package comprises coupling a photoresist layer to a non-device side of a semiconductor wafer, the semiconductor wafer having a device side, first and second circuits formed in the device side and separated by a scribe street, a test device positioned in the scribe street. The method also comprises coupling a tape to the device side of the semiconductor wafer. The method also comprises performing a photolithographic process to form an opening in the photoresist layer and plasma etching through the semiconductor wafer by way of the opening in the photoresist layer to produce first and second semiconductor dies having the first and second circuits, respectively. The method also comprises removing the tape from device sides of the first and second semiconductor dies, wherein removing the tape includes removing the test device. The method also comprises coupling the first circuit of the first semiconductor die to a conductive member. The method also comprises covering the first semiconductor die with a mold compound, the conductive member exposed to an exterior surface of the mold compound.


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