The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Apr. 04, 2023
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

John Eric Linstadt, Palo Alto, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G06F 11/1012 (2013.01); G06F 11/1016 (2013.01); G06F 11/1032 (2013.01); G06F 11/1048 (2013.01); G11C 29/1201 (2013.01); G11C 29/18 (2013.01); G11C 29/4401 (2013.01);
Abstract

A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.


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