Memory operation method for unaligned write, memory and electronic device

Abstract

Disclosed are a memory operating method, memory and electronic device. The memory follows a read-write parallel protocol and includes a plurality of memory banks, and the method comprises: writing data to a specified location of the first memory bank corresponding to a current logical address, and pre-reading original data in a specified location of the second memory bank corresponding to a next logical address in a current clock cycle; encoding the pre-read original data and data to be written next, when an instruction to encode based on the pre-read original data in a next clock cycle is obtained; and writing the encoded data to the specified location of the second memory bank in the next clock cycle. By pre-reading the original data corresponding to the incremental address in the current clock cycle, the present disclosure can accelerate an encoding operation that may occur next.