The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Nov. 24, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ashim Dutta, Clifton Park, NY (US);

Shyng-Tsong Chen, Rensselaer, NY (US);

Terry A. Spooner, Mechanicville, NY (US);

Chih-Chao Yang, Glenmont, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/16 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); G11C 11/161 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H10B 61/00 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02);
Abstract

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in dielectric material. A dielectric cap layer is formed on exposed surfaces of the memory area and the non-memory area. A bottom metal contact is formed on a first metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench in the dielectric cap layer. A memory element stack pillar is formed on the bottom metal contact. A dielectric layer is formed on exposed surfaces of the memory area and the non-memory area utilizing a non-conformal deposition process. The dielectric layer is removed from sidewalls of the memory element stack pillar.


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