The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2025
Filed:
Aug. 19, 2024
Semiconductor device including backside contact structure with silicide layer formed in feol process
Samsung Electronics Co., Ltd., Suwon-si, KR;
Wonkeun Chung, Clifton Park, NY (US);
Byounghoon Kim, Rexford, NY (US);
Jongjin Lee, Clifton Park, NY (US);
Kang-Ill Seo, Springfield, VA (US);
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Abstract
Provided is a semiconductor device including backside contact structure with a silicide layer formed in an FEOL process, and a method of manufacturing the same. The method includes: forming a channel structure on a substrate; forming a placeholder structure in the substrate; forming a silicide layer on the placeholder structure; forming a source/drain region on the silicide layer based on the channel structure; forming a gate structure on the channel structure; and forming a backside contact structure on a bottom surface of the placeholder structure.