The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Apr. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chun-Fai Cheng, Hong Kong, TW;

Chang-Miao Liu, Hsinchu, TW;

Ming-Lung Cheng, Kaohsiung County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/28 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H10D 64/017 (2025.01); H01L 21/28123 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/679 (2025.01);
Abstract

Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing fin-shaped active regions protruding from a substrate, forming cladding layers extending along sidewalls of the fin-shaped active regions, forming a dielectric feature over the substrate to fill space between two adjacent cladding layers, forming a gate structure over channel regions of the fin-shaped active regions and over a first portion of the cladding layers, performing an etching process to remove a second portion of the cladding layers not covered by the gate structure to form sidewall spacer trenches, forming a dielectric spacer in each of the sidewall spacer trenches, and after the forming of the dielectric spacers, forming source/drain features.


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