The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Mar. 14, 2023
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Wei-Lin Wang, Taichung, TW;

Michio Sakurai, Hsinchu, TW;

Cheng Yu Tsai, Hsinchu County, TW;

Shou-Zen Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/68 (2025.01); H01G 4/018 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H10D 1/696 (2025.01); H01G 4/018 (2013.01); H01L 23/5223 (2013.01);
Abstract

A semiconductor structure including the following components is provided. A first capacitor structure includes first, second, and third electrode layers and first and second dielectric layers. The second electrode layer is disposed on the first electrode layer. The top-view pattern of the second electrode layer partially overlaps the top-view pattern of the first electrode layer to have a first overlapping region. The third electrode layer is disposed on the second electrode layer. The top-view pattern of the third electrode layer partially overlaps the top-view pattern of the second electrode layer to have a second overlapping region. The first overlapping region and the second overlapping region have the same top-view area. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The second dielectric layer is disposed between the second electrode layer and the third electrode layer.


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