The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Jun. 02, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Assaf Ben-Bassat, Haifa, IL;

Ofir Degani, Nes-Ammin, IL;

Anna Nazimov, Haifa, IL;

Naor Shay, Rehovot, IL;

Ina Shternberg, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/38 (2015.01); H03K 19/0948 (2006.01); H03K 19/20 (2006.01); H03M 1/66 (2006.01); H04B 1/40 (2015.01);
U.S. Cl.
CPC ...
H04B 1/40 (2013.01); H03K 19/0948 (2013.01); H03K 19/20 (2013.01); H03M 1/66 (2013.01);
Abstract

Techniques are described to address P-MOS bias temperature instability (BTI) stress issues within capacitive radio frequency digital-to-analog converter (CDAC) using a circuit architecture solution that functions to protect the transistors in various operating conditions. Techniques are disclosed that function to float one or both of the negative and positive power supply rail voltages higher or lower, respectively, for CDAC cells depending upon various operating scenarios. These scenarios include the transmitting state of individual CDAC cells and the transmitting state of the CDAC array in which the CDAC cell is implemented.


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