The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Jun. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chia-Tien Wu, Taichung, TW;

Wei-Cheng Lin, Taichung, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/49805 (2013.01); H01L 23/53209 (2013.01); H01L 21/76801 (2013.01); H01L 21/76805 (2013.01); H01L 23/53219 (2013.01); H01L 23/53223 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 23/53247 (2013.01); H01L 23/53252 (2013.01); H01L 23/53257 (2013.01); H01L 23/53266 (2013.01); H01L 25/0655 (2013.01); H01L 2221/1015 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01);
Abstract

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, an isolation layer, a first electronic device, a first interconnection structure, a first conductive structure, and a second conductive structure. The substrate has a first surface and a second surface opposite the first surface. The isolation layer contacts the second surface of the substrate and has a first surface facing away from the substrate. The first electronic device is embedded in the substrate. The first interconnection structure extends from the first surface of the substrate to the first surface of the isolation layer. The first conductive structure is disposed on the first surface of the substrate. The second conductive structure contacts the first surface of the isolation layer. The first conductive structure and the second conductive structure are electrically connected by the first interconnection structure.


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