The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Aug. 07, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd, Hsinchu, TW;

Inventors:

Wei-Kuan Yen, Hsinchu, TW;

Yi-Cheng Chiu, Taipei, TW;

Yen-Chiang Liu, Hsinchu, TW;

Kang-Tai Peng, Zhubei, TW;

Jui-Chun Weng, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G01R 31/28 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); G01R 31/2884 (2013.01); G01R 31/2894 (2013.01); H01L 22/20 (2013.01); H10D 84/013 (2025.01); H10D 84/0156 (2025.01); H10D 84/017 (2025.01); H10D 84/0191 (2025.01); H10D 84/038 (2025.01);
Abstract

In a method of fabricating at least one IC, doped regions are formed on a semiconductor wafer using a first photolithography mask, including at least one doped region of a test structure. Active regions are formed on the semiconductor wafer using a second photolithography mask, including active regions of the test structure. Electrical contacts are formed on the active regions of the test structure. Electrical resistances are measured between pairs of active regions of the test structure using the electrical contacts. At least one metric is determined indicating whether the doped regions are spatially aligned with the active regions based on the measured electrical resistances. In response to the at least one metric indicating the doped regions are spatially aligned with the active regions, completing fabrication of the at least one integrated circuit.


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