The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Feb. 04, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sun Young Noh, Hwaseong-si, KR;

Eui Bok Lee, Seoul, KR;

Wan Don Kim, Seongnam-si, KR;

Han Min Jang, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); H01L 21/76832 (2013.01); H01L 21/76843 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01);
Abstract

A semiconductor device includes: a substrate; a first interlayer insulating layer on the substrate; a first wiring pattern in a first trench of the first interlayer insulating layer; a second interlayer insulating layer on the first interlayer insulating layer; a second wiring pattern in a second trench of the second interlayer insulating layer; a third interlayer insulating layer on the second interlayer insulating layer; a third wiring pattern in a third trench of the third interlayer insulating layer, and including a wiring barrier layer and a wiring filling layer, wherein the wiring filling layer contacts the third interlayer insulating layer; a via trench extending from the first wiring pattern to the third trench; and a via including a via barrier layer and a via filling layer. The via barrier layer is in the via trench. The via filling layer contacts the first wiring pattern and the wiring filling layer.


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