The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Jun. 16, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Runping Wu, Hefei, CN;

Taegyun Kim, Hefei, CN;

Daejoong Won, Hefei, CN;

Soonbyung Park, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/32 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76205 (2013.01); H01L 21/32 (2013.01); H01L 21/76224 (2013.01);
Abstract

Embodiment relates to a semiconductor structure and a fabrication method thereof. The method for fabricating a semiconductor structure includes: providing a substrate including an array region and a peripheral region connected to the array region; arranging a plurality of pads on the array region, an isolation trench being formed between adjacent two of the plurality of pads; and forming a to-be-etched path layer on a sidewall of the isolation trench. In the method for fabricating a semiconductor structure, after the plurality of pads are formed, a to-be-etched path layer is formed on a sidewall of the isolation trench between the plurality of pads. The to-be-etched path layer may be in contact with a to-be-etched material layer in the array region. After a flat surface is formed on the array region and the peripheral region, the to-be-etched path layer and the to-be-etched material layer may be removed in sequence.


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