The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Aug. 10, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kunal R. Parekh, Boise, ID (US);

Glen E. Hush, Boise, ID (US);

Sean S. Eilert, Penryn, CA (US);

Aliasger T. Zaidy, Seattle, WA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G16B 30/00 (2019.01); G16B 50/10 (2019.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G06F 3/0656 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G11C 7/08 (2013.01); G11C 7/1039 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G16B 30/00 (2019.02); G16B 50/10 (2019.02); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 24/08 (2013.01); H01L 24/48 (2013.01); H01L 24/80 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); G06F 2213/28 (2013.01); H01L 24/16 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/1601 (2013.01); H01L 2224/16221 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48221 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14335 (2013.01); H01L 2924/1436 (2013.01);
Abstract

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.


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