The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Aug. 15, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Anirban Ray, Santa Clara, CA (US);

Parag R. Maharana, Dublin, CA (US);

Gurpreet Anand, Pleasanton, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0802 (2016.01); G06F 9/50 (2006.01); G06F 12/02 (2006.01); G06F 16/958 (2019.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 9/5077 (2013.01); G06F 12/0238 (2013.01); G06F 16/972 (2019.01);
Abstract

A computing system having at least one bus, a plurality of different memory components, and a processing device operatively coupled with the plurality of memory components through the at least one bus. The different memory components include first memory and second memory having different memory access speeds. The computing system further includes a memory virtualizer operatively to: store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory; and swap data content in the first memory and the second memory according to adjustments to the address map.


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