The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2025
Filed:
Feb. 15, 2022
Brewer Science, Inc., Rolla, MO (US);
Chia-Hsin Lee, Taoyuan, TW;
Alice Guerrero, Overijse, BE;
Arthur O. Southard, St. James, MO (US);
Chen-Yu Wu, Taipei, TW;
Xiao Liu, Chandler, AZ (US);
Brewer Science, Inc., Rolla, MO (US);
Abstract
Achieving homogeneous and heterogeneous integration for 2.5D and 3D integrated circuit, chip-to-wafer, chip-to-substrate, or wafer-to-wafer bonding is an essential technology. The landing wafer or substrate is bonded with a carrier by using a temporary bonding material before thinning the landing wafer to the desired thickness. Upon completion of redistribution layer formation, Cu pad formation, or other backside processing, dies or wafers with through-silicon vias are stacked onto the landing substrate before molding and singulation. As the landing wafer usually has interconnection metals in the bond line, and those interconnection metals are typically made from lead-free solder alloys, deformation of those solder alloys during thermocompression bonding becomes an issue for manufacturers. To address this issue, a polymeric material with desired strengths is coated on the device wafer to form a conformal protective layer on top of solder alloys, thus enabling temporary bonding and debonding processes.