Through-dielectric-vias (tdvs) for 3d integrated circuits in silicon

Abstract

Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon are provided. Example structures and processes fabricate conductive vertical pillars for an integrated circuit assembly in a volume of dielectric material instead of in silicon. For example, a block of a silicon substrate may be removed and replaced with dielectric material, and then a plurality of the conductive pillars can be fabricated through the dielectric block. The through-dielectric-vias are shielded from devices and from each other by an intervening thickness of the dielectric sufficient to reduce noise, signal coupling, and frequency losses. The through-dielectric-vias can provide improved stress management and reduced keep-out-zones, reduced via-to-via and via-to-device coupling because of relatively large dielectric spacing and low-k dielectrics that can be used, reduced parasitic capacitance, faster switching speeds, lower heat dissipation requirements, lower production costs, easy miniaturization that is scalable to large assemblies and interposers, and high performance stacked assemblies.