The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Aug. 11, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Jingwen Lu, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76895 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 23/53266 (2013.01); H01L 23/53271 (2013.01);
Abstract

Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate having a plurality of active area; forming a plurality of bit lines arranged at intervals on the substrate, the plurality of bit lines having a plurality of first mask layers; forming a first dielectric layer on the substrate positioned between adjacent two of the plurality of bit lines; patterning the first dielectric layer, to form a plurality of first notches arranged at intervals on the first dielectric layer; forming a second mask layer on the first dielectric layer, and the second mask layer encircling in each of the plurality of first notches to form a second notch; forming a plurality of contact holes arranged at intervals in the first dielectric layer; and forming a conductive plunger in each of the plurality of contact holes.


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