The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Aug. 03, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsiang-Wei Liu, Hsinchu, TW;

Andy Yang, Hsinchu, TW;

Yao-Jen Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/18 (2006.01); G11C 5/02 (2006.01); G11C 17/16 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10B 20/25 (2023.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 5/025 (2013.01); G11C 17/16 (2013.01); H01L 21/76802 (2013.01); H01L 23/5226 (2013.01); H10B 20/25 (2023.02);
Abstract

An integrated circuit (IC) device includes transistor and programmable structure regions. The transistor region includes a source structure configured to receive a reference voltage, a first portion of a drain structure, and a gate electrode positioned between the source structure and the first portion of the drain structure, and configured to receive an activation signal. The programmable structure region includes a second portion of the drain structure, a first signal line configured to receive an operational voltage, a second signal line, a gate via underlying and electrically connected to the first signal line, and a drain via positioned between and electrically connected to the second portion of the drain structure and the second signal line. Portions of the first signal line including a gate via location and the second signal line including a drain via location are positioned in parallel in a same metal layer of the IC device.


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