The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Sep. 20, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Thomas Willhalm, Sandhausen, DE;

Francesc Guim Bernat, Barcelona, ES;

Karthik Kumar, Chandler, AZ (US);

Rita Gupta, Cedar Park, TX (US);

Mark Schmisseur, Phoenix, AZ (US);

Dimitrios Ziakas, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/20 (2006.01); G06F 9/445 (2018.01); G06F 9/50 (2006.01); G06F 11/14 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2023 (2013.01); G06F 9/44505 (2013.01); G06F 9/5016 (2013.01); G06F 11/1441 (2013.01); G06F 12/1425 (2013.01); G06F 12/1466 (2013.01);
Abstract

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.


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