The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2025
Filed:
Dec. 22, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Mahesh K. Kumashikar, Bangalore, IN;
Md Altaf Hossain, Portland, OR (US);
Mahesh A. Iyer, Fremont, CA (US);
Yuet Li, Fremont, CA (US);
Atul Maheshwari, Portland, OR (US);
Ankireddy Nalamalpu, Portland, OR (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 19/042 (2006.01);
U.S. Cl.
CPC ...
G05B 19/042 (2013.01); G05B 2219/21155 (2013.01);
Abstract
Systems or methods of the present disclosure may provide efficient power consumption for programmable logic devices based on reducing guardband voltages. A programmable logic device may include circuit monitors to mimic critical paths of an implemented circuit design and generate timing information based on the critical paths. A controller on the programmable logic device may adjust the voltage guardband based on the timing information.