The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Nov. 25, 2024
Applicant:

Monolithic 3d Inc., Klamath Falls, OR (US);

Inventors:

Zvi Or-Bach, Haifa, IL;

Brian Cronquist, Klamath Falls, OR (US);

Assignee:

Monolithic 3D Inc., Klamath Falls, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 88/00 (2025.01); G03F 9/00 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/544 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01); H10B 20/00 (2023.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01); H10D 10/01 (2025.01); H10D 10/40 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/83 (2025.01); H10D 30/87 (2025.01); H10D 62/83 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 84/90 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01); H10D 89/10 (2025.01); H01L 21/268 (2006.01); H01L 23/00 (2006.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 88/00 (2025.01); G03F 9/7076 (2013.01); G03F 9/7084 (2013.01); H01L 21/76254 (2013.01); H01L 21/76898 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/544 (2013.01); H10B 10/00 (2023.02); H10B 10/125 (2023.02); H10B 12/053 (2023.02); H10B 12/09 (2023.02); H10B 12/50 (2023.02); H10B 20/00 (2023.02); H10B 41/20 (2023.02); H10B 43/20 (2023.02); H10D 10/051 (2025.01); H10D 10/40 (2025.01); H10D 30/0512 (2025.01); H10D 30/061 (2025.01); H10D 30/6727 (2025.01); H10D 30/6728 (2025.01); H10D 30/6733 (2025.01); H10D 30/6735 (2025.01); H10D 30/6737 (2025.01); H10D 30/6743 (2025.01); H10D 30/83 (2025.01); H10D 30/87 (2025.01); H10D 62/83 (2025.01); H10D 64/027 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 84/907 (2025.01); H10D 84/998 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01); H10D 88/01 (2025.01); H10D 89/10 (2025.01); H01L 21/268 (2013.01); H01L 24/73 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1301 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3025 (2013.01); H10D 64/017 (2025.01); H10D 84/83 (2025.01);
Abstract

A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.


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