The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Dec. 13, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chao-Ching Cheng, Hsinchu, TW;

Wei-Sheng Yun, Taipei, TW;

I-Sheng Chen, Hsinchu, TW;

Shao-Ming Yu, Hsinchu County, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Chih Chieh Yeh, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 30/62 (2025.01); H10D 62/17 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 64/685 (2025.01); H10D 30/62 (2025.01); H10D 62/235 (2025.01); H10D 84/0128 (2025.01); H10D 84/0144 (2025.01); H10D 84/0167 (2025.01); H10D 84/0177 (2025.01); H10D 84/0181 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/8311 (2025.01); H10D 84/8314 (2025.01); H10D 84/832 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01); H10D 84/856 (2025.01); H10D 64/017 (2025.01); H10D 84/0158 (2025.01);
Abstract

A semiconductor device includes a substrate having an I/O region and a core region; a first transistor in the I/O region; and a second transistor in the core region, wherein the first transistor includes a first gate structure having: an interfacial layer; a first high-k region over the interfacial layer; and a conductive layer over the first high-k region, wherein the second transistor includes a second gate structure having: the interfacial layer; a second high-k region over the interfacial layer; and the conductive layer over the second high-k region, and where in the first high-k region is thicker than the second high-k region.


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