The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Jan. 12, 2022
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

National Yang Ming Chiao Tung University, Hsinchu, TW;

Inventors:

Yu-Che Chou, Yilan County, TW;

Li-Cheng Teng, Hsinchu, TW;

Wan-Hsuan Chung, Taichung, TW;

Chao-Hsin Chien, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10D 30/69 (2025.01); H10D 30/031 (2025.01); H10D 30/0413 (2025.01); H10D 30/0415 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 30/701 (2025.01); H10D 62/118 (2025.01); H10N 70/063 (2023.02); H10N 70/253 (2023.02);
Abstract

An integrated circuit device includes a semiconductor substrate, a first gate structure, a channel layer, source and drain features, a second gate structure, a first contact, and a second contact. The first gate structure is over the semiconductor substrate. The first gate structure includes a gate dielectric layer and a first gate electrode. The channel layer is over and surrounded by the first gate structure. The source and drain features are respectively on opposite first and second sides of the channel layer. The second gate structure is over the channel layer. The second gate structure includes a programming gate dielectric layer having a data storage layer and a second gate electrode over the programming gate dielectric layer. The first gate contact is on the first gate electrode. The second gate contact is on the second gate electrode.


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