The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Oct. 17, 2022
Applicant:

Seriphy Technology Corporation, Hsinchu County, TW;

Inventors:

Tzu-Wei Chiu, Hsinchu County, TW;

Chun-Wei Chang, Taipei, TW;

Shang-Pin Chen, Hsinchu County, TW;

Wei-Chih Chen, Taoyuan, TW;

Che-Yen Huang, Hsinchu County, TW;

Assignee:

SERIPHY TECHNOLOGY CORPORATION, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 24/08 (2013.01); H01L 2224/08145 (2013.01);
Abstract

The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.


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