The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Mar. 14, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Harry-Hak-Lay Chuang, Zhubei, TW;

Wei-Cheng Wu, Zhubei, TW;

Wen-Tuo Huang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/76898 (2013.01); H01L 22/12 (2013.01); H01L 22/32 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/8083 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06596 (2013.01);
Abstract

Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.


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