The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

May. 26, 2022
Applicant:

Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);

Inventors:

Cyprian Emeka Uzoh, San Jose, CA (US);

Guilian Gao, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31111 (2013.01); H01L 21/02057 (2013.01); H01L 21/31133 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 21/76813 (2013.01); H01L 21/76816 (2013.01); H01L 21/76832 (2013.01); H01L 21/76865 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68381 (2013.01);
Abstract

Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.


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