The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

May. 20, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jeremy M. Hirst, Orangevale, CA (US);

Shanky K. Jain, Folsom, CA (US);

Hernan A. Castro, Shingle Springs, CA (US);

Richard K. Dodge, Santa Clara, CA (US);

William A. Melton, Shingle Springs, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G06F 16/21 (2019.01); G06F 16/587 (2019.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 16/12 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/34 (2013.01); G06F 16/219 (2019.01); G06F 16/587 (2019.01); G11C 11/5614 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G11C 16/12 (2013.01); G11C 16/26 (2013.01); G11C 2213/77 (2013.01);
Abstract

The present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.


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