The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Feb. 23, 2022
Applicant:

Ansys, Inc., Canonsburg, PA (US);

Inventors:

Qian Shen, Southborough, MA (US);

Joao Geada, Chelmsford, MA (US);

Assignee:

ANSYS, INC., Canonsburg, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 30/3312 (2020.01);
U.S. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 30/3312 (2020.01);
Abstract

According to one aspect of this disclosure, time domain information can be associated with switching probabilities and propagated through a simulated circuit during a static timing analysis to provide finer grain details for use by a power analysis of the simulated circuit (such as a dynamic voltage drop analysis or simulation). Signal correlations may also be propagated with the associated time domain information to provide further finer details for use in power analysis. A method according to one embodiment can include: determining, for each input pin of an aggressor element, a set of one or more time dependent input switching probabilities during a set of one or more corresponding timing windows in a simulated representation of a circuit; determining, from each time dependent input switching probability of each timing window, a set of time dependent output switching probabilities at an output pin of the aggressor element; and performing a power analysis for one or more victim circuit elements that are coupled to the aggressor element, the power analysis based on the set of time dependent output switching probabilities at the output pin of the aggressor element.


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