The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Dec. 15, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rahul Pal, Bangalore, IN;

Aravindh Anantaraman, Folsom, CA (US);

Lakshminarayana Pappu, Folsom, CA (US);

Dongsheng Bi, Fremont, CA (US);

Guadalupe J. Garcia, Chandler, AZ (US);

Altug Koker, El Dorado Hills, CA (US);

Joydeep Ray, Folsom, CA (US);

Rahul Joshi, Pune, IN;

Shrikul Atulkumar Joshi, Rajkot, IN;

Mahak Gupta, Bengaluru, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0871 (2016.01); G06F 12/0891 (2016.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0871 (2013.01); G06F 12/0891 (2013.01); G06F 13/1668 (2013.01); G06F 13/28 (2013.01); G06F 15/7807 (2013.01);
Abstract

In a further embodiment, a system on a chip integrated circuit (SoC) is provided that includes an active base die including a first cache memory, a first die mounted on and coupled with the active base die, and a second die mounted on the active base die and coupled with the active base die and the first die. The first die includes an interconnect fabric, an input/output interface, and an atomic operation handler. The second die includes an array of graphics processing elements and an interface to the first cache memory of the active base die. At least one of the graphics processing elements are configured to perform, via the atomic operation handler, an atomic operation to a memory device.


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