The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Dec. 27, 2022
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Weiwei Chen, Boston, MA (US);

Raghu Prabhakar, San Jose, CA (US);

David Alan Koeplinger, Egg Harbor Township, NJ (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 8/41 (2018.01); G06F 5/08 (2006.01); G06F 9/38 (2018.01); G06F 15/82 (2006.01);
U.S. Cl.
CPC ...
G06F 8/453 (2013.01); G06F 5/08 (2013.01); G06F 8/433 (2013.01); G06F 8/441 (2013.01); G06F 8/458 (2013.01); G06F 9/3869 (2013.01); G06F 15/825 (2013.01);
Abstract

The technology disclosed provides a system that comprises a processor with computing units on an integrated circuit substrate. The processor is configured to map a program across multiple hardware stages with each hardware stage executing a corresponding operation of the program at a different stage latency dependent on an operation type and an operand format. The system further comprises a runtime logic that configures the compute units with configuration data. The configuration data causes first and second producer hardware stages in a given compute unit to execute first and second data processing operations and produce first and second outputs at first and second stage latencies, and synchronizes consumption of the first and second outputs by a consumer hardware stage in the given compute unit for execution of a third data processing operation by introducing a register storage delay that compensates for a difference between the first and second stage latencies.


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