The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Apr. 16, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Marcus Johannes Henricus Van Dal, Linden, BE;

Gerben Doornbos, Kessel-Lo, BE;

Georgios Vallianitis, Heverlee, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 62/17 (2025.01); H10D 62/80 (2025.01); H10D 64/27 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6757 (2025.01); H10D 30/6755 (2025.01); H10D 62/292 (2025.01); H10D 62/875 (2025.01); H10D 64/512 (2025.01); H10D 64/518 (2025.01); H10D 64/519 (2025.01); H10D 88/00 (2025.01);
Abstract

A transistor, an integrated semiconductor device, and methods of making the same are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layerhas a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.


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