The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Aug. 07, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Ming-Yen Chuang, Hsinchu, TW;

Katherine H. Chiang, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 53/30 (2023.01); H01L 21/02 (2006.01); H10D 30/67 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10B 53/30 (2023.02); H01L 21/02565 (2013.01); H10D 30/6728 (2025.01); H10D 30/6755 (2025.01); H10D 99/00 (2025.01);
Abstract

A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.


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