The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Jun. 11, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Jun Xia, Hefei, CN;

Tao Liu, Hefei, CN;

Qiang Wan, Hefei, CN;

Jungsu Kang, Hefei, CN;

Kangshu Zhan, Hefei, CN;

Sen Li, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/033 (2023.02); H01L 21/0274 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H10B 12/09 (2023.02); H10B 12/31 (2023.02); H10B 12/50 (2023.02);
Abstract

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, where the substrate includes a complete die region and an incomplete die region; forming a stack on the substrate, where the stack includes sacrificial layers and supporting layers; forming a first photoresist layer on the stack; exposing the first photoresist layer, and developing to remove the first photoresist layer on the incomplete die region; and etching the stack by using the first photoresist layer on the complete die region as a mask.


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