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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12368139 B1

PDFFull Text
Date of Patent:
Jul. 22, 2025

Filed:

Feb. 25, 2022

Structures for providing electrical isolation in semiconductor devices

Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Chan-Hong Chern, Palo Alto, CA (US);

Mark Chen, Hsinchu County, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Attorney:

Jones Day

Primary Examiner:

Julio J Maldonado

Assistant Examiner:

Stanetta D Isaac

Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 21/02 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01);
U.S. Cl.
CPC ...
H01L 25/072 (2013.01); H01L 21/0254 (2013.01); H01L 21/4853 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49844 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H10D 30/015 (2025.01); H10D 30/4755 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01); H01L 2224/16225 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10344 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15738 (2013.01); H01L 2924/381 (2013.01);
Abstract

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.

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