The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2025
Filed:
Mar. 14, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Chun-Chieh Fang, Chiayi County, TW;
Chien-Chang Huang, Tainan, TW;
Chi-Yuan Wen, Tainan, TW;
Jian Wu, Shanghai, CN;
Ming-Chi Wu, Kaohsiung, TW;
Jung-Yu Cheng, Tainan, TW;
Shih-Shiung Chen, Tainan, TW;
Wei-Tung Huang, Tainan, TW;
Yu-Lung Yeh, Kaohsiung, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.