Reference voltage adjustment per path for high speed memory signaling

Abstract

In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path.