The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Nov. 06, 2023
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

Thomas Vogelsang, Mountain View, CA (US);

Michael Raymond Miller, Raleigh, NC (US);

Collins Williams, Raleigh, NC (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4093 (2006.01); G06F 12/0895 (2016.01); G11C 8/18 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G06F 12/0895 (2013.01); G11C 8/18 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 2207/2245 (2013.01);
Abstract

Disclosed is a memory system including a memory component having at least one tag row and at least one data row and multiple ways to hold a data group as a cache-line or cache-block. The memory system includes a memory controller that is connectable to the memory component to implement a cache and operable with the memory controller and the memory component in each of a plurality of operating modes including a first and second operating mode having differing addressing and timing requirements for accessing the data group. The first operating mode having placement of each of at least two ways of a data group in differing rows in the memory component, with tag access and data access not overlapped. The second operating mode having placement of all ways of a data group in a same row in the memory component, with tag access and data access overlapped.


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