Systems and methods for controlling power assertion in a memory device

Abstract

Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal. The latch circuit may synchronize the local word line sleep signal with the delayed clock signal such that the local word line sleep signal is prevented from turning off power to the word line driver until memory read and write operations of the memory cell are disabled by the word line clock signal.