The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Jul. 17, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Osamu Nagashima, Kanagawa, JP;

Yoshinori Matsui, Kanagawa, JP;

Keun Soo Song, Boise, ID (US);

Hiroki Takahashi, Tokyo, JP;

Shunichi Saito, Kanagawa, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G06F 12/023 (2013.01); G06F 1/08 (2013.01); G06F 1/12 (2013.01); G11C 11/4076 (2013.01);
Abstract

A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.


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