The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2025

Filed:

Oct. 21, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Doron Rajwan, Rishon le-Zion, IL;

Efraim Rotem, Haifa, IL;

Eliezer Weissmann, Haifa, IL;

Avinash N. Ananthakrishnan, Portland, OR (US);

Dorit Shapira, Atlit, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3228 (2019.01); G06F 1/3203 (2019.01); G06F 1/3237 (2019.01); G06F 1/324 (2019.01); G06F 1/3234 (2019.01); G06F 1/3293 (2019.01); G06F 30/34 (2020.01); G06F 119/06 (2020.01); G06F 119/08 (2020.01);
U.S. Cl.
CPC ...
G06F 1/3228 (2013.01); G06F 1/3203 (2013.01); G06F 1/3237 (2013.01); G06F 1/324 (2013.01); G06F 1/3234 (2013.01); G06F 1/3243 (2013.01); G06F 1/3293 (2013.01); G06F 30/34 (2020.01); G06F 2119/06 (2020.01); G06F 2119/08 (2020.01);
Abstract

In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.


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