The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Feb. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsin Fu Lin, Hsinchu County, TW;

Shiang-Hung Huang, New Taipei, TW;

Tsung-Hao Yeh, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 89/60 (2025.01); H10D 8/00 (2025.01); H10D 8/01 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 89/611 (2025.01); H10D 8/043 (2025.01); H10D 8/411 (2025.01); H10D 62/126 (2025.01);
Abstract

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a well region disposed within a semiconductor substrate and comprises a first doping type. A gate electrode overlies the well region. A first contact region is disposed within the well region and comprises a second doping type opposite the first doping type. A second contact region is disposed within the semiconductor substrate and laterally offset from the well region. The second contact region comprises the first doping type and the gate electrode is disposed between the first contact region and the second contact region. A gate dielectric layer is disposed between the semiconductor substrate and the gate electrode, where a thickness of the gate dielectric layer is greater than about 140 Angstroms.


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