The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Jan. 06, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Chen Zhang, Guilderland, NY (US);

Junli Wang, Slingerlands, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Dechao Guo, Niskayuna, NY (US);

Sung Dae Suk, Watervliet, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H10D 30/62 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10D 84/0193 (2025.01); H10D 30/6215 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 88/00 (2025.01); H10D 88/01 (2025.01);
Abstract

A semiconductor device includes a FinFET fin. The same FinFET fin is associated with a bottom FinFET and a top FinFET. The FinFET fin includes a lower channel portion, associated with the bottom FinFET, a top channel portion, associated with the top FinFET, and a channel isolator between the bottom channel portion and the top channel portion. A lower gate includes a vertical portion that is upon a sidewall of the bottom channel portion. An isolation layer may be formed upon the lower gate if it is desired for the top FinFET fin and the bottom FinFET fin to not share a gate. An upper gate is upon the top channel portion and is further upon the isolation layer, if present, or is upon the lower gate.


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