The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Mar. 10, 2022
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Kenichi Agawa, Yokohama, JP;

Hidetoshi Miyahara, Kawasaki, JP;

Yusuke Imaizumi, Kawasaki, JP;

Atsushi Kurosu, Tokyo, JP;

Atsushi Tomishima, Matsudo, JP;

Jia Liu, Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/552 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 23/49805 (2013.01); H01L 23/49838 (2013.01); H01L 23/5386 (2013.01); H01L 23/552 (2013.01); H01L 24/16 (2013.01); H01L 24/24 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/16267 (2013.01); H01L 2224/24265 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/32267 (2013.01); H01L 2224/48195 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/48265 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/3512 (2013.01);
Abstract

According to one embodiment, a semiconductor device c includes: a package substrate including a base including a mount portion, and terminals; a semiconductor chip including a first pad to which a ground voltage is supplied, a second pad electrically connected to a first terminal among the terminals, and a semiconductor circuit connected to the first and second pads, the semiconductor chip being provided above the mount portion; and a first capacitor chip including a first capacitor unit provided in a silicon substrate, a first node supplied with the ground voltage, and a second node electrically connected to the second pad, the first capacitor chip being provided above the mount portion.


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