The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2025

Filed:

Sep. 28, 2023
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Thomas Paul Leboeuf, Sandia Park, NM (US);

James Anderson, Madison, AL (US);

James D. Wesselkamper, Albuquerque, NM (US);

Jason J. Moore, Albuquerque, NM (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G08B 13/22 (2006.01); G11C 19/28 (2006.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
G08B 13/22 (2013.01); G11C 19/287 (2013.01); H01L 25/18 (2013.01); H10B 80/00 (2023.02); H01L 23/481 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01);
Abstract

An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.


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