The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2025
Filed:
Sep. 26, 2020
Intel Corporation, Santa Clara, CA (US);
Kuljit S. Bains, Olympia, WA (US);
Kjersten E. Criss, Portland, OR (US);
Rajat Agarwal, Portland, OR (US);
Omar Avelar Suarez, Zapopan, MX;
Subhankar Panda, Portland, OR (US);
Theodros Yigzaw, Sherwood, OR (US);
Rebecca Z. Loop, Portland, OR (US);
John G. Holm, Beaverton, OR (US);
Gaurav Porwal, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.