The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

May. 11, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Szu-Wei Tseng, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/0158 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 84/013 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The substrate has a base and a fin structure over the base, and the dielectric layer is over the base and surrounds the fin structure. The method includes forming a gate stack over the fin structure and the dielectric layer. The method includes removing portions of the dielectric layer, which are not covered by the gate stack. The method includes forming first spacers over first sidewalls of the gate stack. The method includes forming second spacers over second sidewalls of the fin structure. The method includes partially removing the fin structure, which is not covered by the gate stack and the first spacers. The method includes forming a source/drain structure over the fin structure, which is not covered by the gate stack and the first spacers.


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