Semiconductor device having low on-resistance and low parasitic capacitance

Abstract

A semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer, a gate electrode, a silicide barrier, a source contact plug, a drain contact plug, and a field plate plug. The gate insulating layer, disposed between the drain region and the source region, includes a first gate insulating layer having a first thickness and a second gate insulating layer having a second thickness larger than the first thickness. A bottom surface of the first gate insulating layer and a bottom surface of the second gate insulating layer are parallel to each other. The gate electrode is disposed on the first and second gate insulating layers. The silicide barrier layer is disposed in contact with a top surface of the second gate insulating layer and a top surface of the gate electrode. The source contact plug is connected to the source region.