The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Sep. 28, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Ardasheir Rahman, Schenectady, NY (US);

Hemanth Jagannathan, Niskayuna, NY (US);

Robert Robison, Rexford, NY (US);

Brent Anderson, Jericho, VT (US);

Heng Wu, Guilderland, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 62/17 (2025.01); H01L 21/76 (2006.01); H10D 30/60 (2025.01); H10D 30/63 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 62/299 (2025.01); H01L 21/76 (2013.01); H10D 30/611 (2025.01); H10D 30/63 (2025.01); H10D 62/151 (2025.01); H10D 64/021 (2025.01); H10D 84/016 (2025.01); H10D 84/038 (2025.01);
Abstract

A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.


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