The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Nov. 24, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Han Lin, Hsinchu, TW;

Chia-En Huang, Hsinchu, TW;

Han-Jong Chia, Hsinchu, TW;

Martin Liu, Hsinchu, TW;

Sai-Hooi Yeong, Hsinchu, TW;

Yih Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 51/30 (2023.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); G11C 11/223 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); H01L 29/6684 (2013.01); H10B 51/30 (2023.02);
Abstract

A method (of writing to a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes: setting the second bit to a logical 1 value, the setting a second bit including applying a gate voltage to the gate terminal, and applying a first source/drain voltage to the second S/D terminal; and wherein the first source/drain voltage is lower than the gate voltage.


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