The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2025

Filed:

Apr. 04, 2022
Applicant:

Stats Chippac Pte. Ltd., Singapore, SG;

Inventors:

Junghwan Jang, Incheon, KR;

Giwoong Nam, Incheon, KR;

Myongsuk Kang, Incheon, KR;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 21/76807 (2013.01); H01L 24/20 (2013.01); H01L 24/94 (2013.01); H01L 2221/1021 (2013.01); H01L 2224/19 (2013.01); H01L 2224/214 (2013.01); H01L 2224/94 (2013.01);
Abstract

A semiconductor device has a semiconductor die. A first dielectric layer is formed over the semiconductor die. A second dielectric layer is formed over the first dielectric layer. A trench is formed in the second dielectric layer. A via opening is formed to expose a contact pad of the semiconductor die within the trench. A seed layer is formed over the second dielectric layer. The seed layer extends into the trench and via opening. A conductive material is deposited into the via opening and trench. The conductive material is overburdened from the trench. The seed layer around the conductive material is etched in a first etching step. The conductive material is etched in a second etching step.


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